The invention relates to a circuit for generating a control signal for the field deflection in a picture display device, comprising a source of incoming synchronizing signals intended for the display of an interlaced picture, and a field identification circuit connected to the synchronizing signal source for producing a first field signal on receipt of a first field and a second field signal on receipt of a subsequent, second field, the second field signal deviating from the first field signal, the first and second field signals forming the control signal and the circuit further comprising an address generator for controlling the transfer of the control signal for the field deflection.
Such a circuit is disclosed in European patent application No. 81.627. In order to reduce an annoying jitter phenomenon on display of a digitally generated picture and/or text information signal, the interlace is eliminated with the aid of this prior art circuit because one field is written on the display screen superimposed on the other field. To that end the circuit comprises a field identification circuit with the aid of which a distinction can be made between the two fields which together form a picture.
It has, however, been found that in certain circumstances, instead of being reduced by the elimination of the interlace, the jitter of the displayed picture is actually increased.